cadence_mixed_signal_ams

Mixed Signal Simulations with AMS Designer (AMSD)
AMS is the new and improved SpectreVerilog, with support for bidirectional pins and other much needed updates. Its easy to run simulations involving behavior/structural verilog __and__ analog BSIM-modeled transistors.

__Text instructions:__
1. **Create a composer schematic** with your verilog symbolic view instantiated as well as at least one transistor. Lets call this cell "test". Save and close. 2. **Create a hierarchy view** (called "config"): 3. **Configure the hierarchy**. You don't need to override the view if the "found view" is what you want. 4. **Open Analog Environment**. 5. Setup the **Connect Rules** which do the A2D and D2A conversion between analog land and digital land. 6. In ADE, add some signals to view. 7. (May or may not be necessary:) In ADE, Simulator -> Netlister and Run Options. Change Netlister mode to OSS-based netlister with irun 8. Run the simulator. 9. Now, let's setup the analog input/output voltages. 10. Run your simulation, the input and output analog voltages should be correct now.
 * Select template, AMS.
 * Change myLib to the libraries you intend to reference.
 * Change the view to schematic.
 * In order to have instances of your verilog modules within other verilog modules, make sure that "verilog" is NOT in the "stop list". This shouldn't be an issue with the AMS template, but it was with SpectreVerilog templates.
 * You should see your submodules in the config view.
 * Change the simulator is AMS.
 * If you haven't added the connectLib library to your Library Manager, add it to cds.lib:
 * DEFINE connectLib $IUSHOME/tools/affirma_ams/etc/connect_lib/connectLib
 * You may need to use AMSHOME if that's how your install is defined.
 * Cadence may need AMSHOME defined - just setenv it equal to $IUSHOME in your cshrc file. IUSHOME should point to the IUS install directory.
 * Set this up in ADE from the menu Setup->Connect Rules.
 * Choose the 18V full fast to start (Select in drop down menu, then click **Add**). Later we can customize for a real supply voltage.
 * You get nothing by default. You can change this to Save All or:
 * As usual, go to Outputs->To Be Plotted->Select On Schematic.
 * It will ask you to save these signals when you run.
 * This solves netlisting problems with some technology libraries.
 * It should run without error and plot your signals afterward.
 * If you want to see what analog voltage is outputted, add a vcvs with unity gain to buffer the digital output into an analog voltage.
 * Supposedly, there are "supply sensitive" connect rules which detect the correct voltages to use. I haven't figured out how to get these to work.
 * To brute force it, again open the Connect Rules page.
 * Pick any connect rule, click customize and then change all of the vsup variables to your supply voltage, and the thresholds to reasonable vdd/3 and vdd*2/3 values. Click change after each time your edit.
 * Finally, click **ok** and it will remind you that you need to click **Add** on the Connect rules page to save your changes.
 * Delete any old connect rules that are listed. You should have only your new customized rules.
 * When you save your ADE state, the connect rules are saved. You can load these in other AMS simulations by only checking the Connect Rules and loading from this saved state.
 * If you know how to use the supply sensitive rules, please update this. I think it may have something to do with Simulation->Options->Netlister (supply0 and ground).

//**__Other Notes:__**//
 * If you edit a verilog file in an outside editor, you must recompile within cadence. Open the verilog file from Library Manager and then type ":wq" to write and quit the editor. The icfb window should say success if your file is error free.
 * If you use an analog lib clock source to drive your verilog, the simulator may have trouble running in digital mode. This would make the simulation very slow. Instead, make a clock generator in verilog. This appears to be fixed in newer versions of Cadence.
 * [[file:clk_gen.v|Example Clock Generator]]
 * You may need **special** text file called hdl.var in the folder where you run cadence
 * Also, make sure you source the necessary setup for Cadence IUS:
 * source /usr/nikola/groups/vlsi/pkgs/cadence_ius/cadence_ius.cshrc

__Pictorial Instructions:__