HDL_synthesis_flow_tutorial

//Be ready with files: (please refer to Dan's synthesis page)//
a. target standard cell lib file for synthesis static184cg_1.5V_25C.db b. target standard cell lib file for place and route cg_lib13.it.lef (make sure use a right one from /n/mead/projects/wsl/stdcell/synthesis_files) c. map file for streaming out gds EncounterOut.map d. map file for steaming into Cadence layout tools cds2gds.map f. icfb standard cell library cg_lib13_wsl (this is a directory that has all the cells in schematic and layout that looks familiar when viewed from Cadence icfb )

**//run design compiler//**
a. create dc command file (ex: mydc ) b. create cmd file ( ex: ) c. mydc bin2Therm this will create bin2Therm_map.v, which is the gate level verilog which gates are instantiated from a target library specified in the .cmd file.

//**run place and route, start**// **encounter** //** **//
Design->Import Design ...



Floorplan->Specify Floorplan ... Power->Power Planning-> Add Ring ... Route->Special Route ... just ok it.

Floorplan->Connect Global Net ... Place->Standard Cells and Blocks ... just ok it.

NanoRoute->Route ... just ok it.

Switch to physical view

Place->Filler->Add fillers ...

Design->Save->GDS

//**Import the synthesized design into Cadence Virtuoso**//
Create a library in icfb and attach the lib to the targeted process.

icfb->File->Import->Stream ...



don't forget to click on "User-Defined Data" and the "options"button on the popups.

Stream in successful????



Open the layout using virtuoso Layout editor

Things observed: The standard cells are not linked correctly. How to fix: a. make sure cg_lib13_wsl is properly specified in your cds.lib b. Layout editor->Edit->Search ... (make sure in LSW window, everything is selectable and visible)

//**Note: the picture below is outdated; the last field should specify cg_lib13_wsl instead of cg_lib13.**// hit push bottom, and then close it. This will replace all the cells of instances with "certain" exceptions using cells defined in cg_lib13_wsl. Here is how the layout looks like now. Things observed: pins are not connected properly. How to fix: a. remove extra labels - Layout Editor->IBM_PDK->LSW->Present Layers Only b. make text invisible. c. make three pin layers selectable and select pins inside the layout(not the ones we want to keep) and delete them.

d. Create->Create pins from Label ... click ok to use the default setting. e. select pin object in LSW

If you select a pin, you will notice there are three objects. The first two are what we imported in the gds. A rectangle and a text label on the metal pin layers. The third object is a pin instance, which we created with the pins from labels tool. You will notice that this has connectivity information, which was inferred from the text label. It is this connectivity info that LVS uses to compare to your schematic.

e. fix the half pins run the skill file: (at the command line window in icfb main window) by:

load("CoverPinsWithMetal.il") CoverPinsWithMetal("//lib//" "//cell//")

This will fix the half sized pins.

Save and run DRC. Fix any remaining issues.

Next we will generate schematics for LVS.

**//Import the gate level netlist (in .v format) into Cadence icfb (for simulation, lvs, etc.)//**
icfb->File->Import->Verilog...

Using schematic editor to open the schematic: You made it!

**//Run LVS.//**
=Multiple power supplies=

By default these cells use vdd! and gnd!. You can edit the netset properties of the cell instances to specify other power supplies.

Sometimes you want to specify a power supply for multiple cells //en masse//, e.g. all the standard cells on a schematic page. To do so:
 * Select all the cells of interest
 * Hit 'q' for properties
 * At the top of the properties form choose the following options:
 * all selected
 * instance
 * any masters
 * Then add the desired netSet property (and preferably select 'display both' for the property)
 * Hit OK or apply