cadence_mixed_signal

Mixed Signal Simulations with SpectreVerilog
Its easy to run simulations involving behavior/structural verilog __and__ analog BSIM-modeled transistors.

__Text instructions:__
1. **Create a composer schematic** with your verilog symbolic view instantiated as well as at least one transistor. Lets call this cell "test". Save and close. 2. **Create a hierarchy view** (called "config"): 3. **Configure the hierarchy**. You don't need to override the view if the "found view" is what you want. 4. **Open the schematic** from the hierarchy editor or by double clicking on the config view. 5. **Open Analog Environment**.
 * Select template, SpectreVerilog.
 * Change myLib to the libraries you intend to reference.
 * In order to have instances of your verilog modules within other verilog modules, make sure that "verilog" is NOT in the "stop list".
 * You should see your submodules in the config view.
 * Go to the Mixed Signal menu -> Interface Elements -> Library.
 * Change the output voltages to your supply voltages for the analog section (I used vdd and 0).
 * For the input voltages, I used vdd/3 and 2*vdd/3 for the thresholds.
 * Make sure the simulator is SpectreVerilog. You should be ready to go!
 * Note that two output logs are produced, one for analog, one for digital.
 * If the simulation appears to hang, check the digital log for errors.

//**__Other Notes:__**//
 * If you edit a verilog file in an outside editor, you must recompile within cadence. Open the verilog file from Library Manager and then type ":wq" to write and quit the editor. The icfb window should say success if your file is error free.
 * If you use an analog lib clock source to drive your verilog, the simulator may have trouble running in digital mode. This would make the simulation very slow. Instead, make a clock generator in verilog. This appears to be fixed in newer versions of Cadence.
 * [[file:clk_gen.v|Example Clock Generator]]
 * You may need empty text file called hdl.var in the folder where you run cadence
 * There is another tutorial on the web [|here.] in case you don't like this one :)
 * Also, make sure you source the necessary setup script for Cadence IUS:
 * source /usr/nikola/groups/vlsi/pkgs/cadence_ius/cadence_ius.cshrc

__Pictorial Instructions:__
















Run your simulation! Note that two output logs are produced, one for the analog simulator (Spectre) and one for the digital simulator (VERILOG-XL). If the simulation appears to hang, check the digital log for errors.