synthesis_flow_ibm013

Synthesis Flow for IBM013
This page is organized as a flow for setting up the tools and going through the synthesis flow. If you have troubles, look for known problems sections.

Environment Setup
Add to .cshrc.local:

source /usr/nikola/groups/vlsi/pkgs/modelsim/modelsim.cshrc source /usr/nikola/groups/vlsi/pkgs/synopsys_syn/synopsys_syn.cshrc source /usr/nikola/groups/vlsi/pkgs/cadence_soc/soc.cshrc source /usr/nikola/groups/vlsi/pkgs/cadence_ius/cadence_ius.cshrc
 * 1) Source modelsim - run with 'vsim'
 * 1) Source synopsis synthesis
 * 1) encounter place and route + cadence RTC compiler
 * 1) source ncverilog / verilogams for cadence

Create a Design
> todo: using modelsim link > todo: using ncverliog link > todo: using vcs link

Copy Synthesis Flow Files
Copy this folder - it is a working directory for synthesizing your design: /n/mead/projects/wsl/stdcell/synthesis_files Add the following line to your cds.lib:  DEFINE cg_lib13_wsl /n/mead/projects/wsl/stdcell/Projects/IBM13/Designs/cg_lib13_wsl

Using Design Vision (Synopsys Synthesis Program)
The synthesis process is handily encapsulated into a shell script called 'synth'. To run on my top.v file, I would call 'synth top' The synth script uses 'top.cmd'. This imports and compiles each file in your design. To adapt for your design, rename top.cmd to [your verilog file name].cmd and edit the cmd file to point towards your designs.

//Known Problems://
 * Failures are often due to verilog code that cannot be represented by hardware (synthesized). Search google for some tips on writing synthesizable code and try to envision the hardware that your code should create as you write the verilog code.
 * Sometimes moving all the combinational logic out of the edge triggered code (@ posedge...) and into always blocks helps the compiler figure things out.

Using RTL Compiler (Cadence Synthesis Program)
The synthrc script works like the synth script, calling the rtl compiler to run your command file (called top.rc instead of top.cmd). The extensions are arbitrary, but the synthrc script should be corrected if you modify the extension.

Using Encounter
The steps to using Encounter are as follows: 1. Import Design 2. Specify Floorplan 3. Set IO Pin Locations 4. Add Power Ring 5. Special Route 6. Place Standard Cells 7. Connect Global Nets 8. NanoRoute 9. Add Fillter 10. Export to GDSII

A tutorial for **TSMC (not IBM)** can be found here: [|Tutorial link] However, the tutorial needs updating to include the following steps for IBM130: The new tutorial is here (in progress).

__Add Filler__ Run Place->Filler->Add Filler Select Cell Name "filler1" and click OK

__Connect Global Nets__ Run Floorplan->Connect Global Nets 1. Check: Tie High, Apply All. Type To Global Net: "vdd!" Click "Add to List" 2. Check: Tie Low, Apply All. Type To Global Net: "gnd!" Click "Add to List"

__Library Updates__ The LEF file during import should be cg_lib13.it.lef During GDS Export, use EncounterOut.map instead of streamOut.map

__Other Tips__ You can leave the row spacing as 0 during Specify Floorplan. This will drastically reduce the layout size. top.io is a pin location specifier file. Easiest thing to do is import your map as usual, export the pin location io file, then edit. top.encounter.cmd is an encounter script you can use. Run with encounter -replay top.encounter.cmd

//Known Problems//:
 * If Encounter crashes when you switch to physical view, you are using an outdated LEF file. See the above section on 'Copying Synthesis Files'
 * There was also an update to the EncounterOut.map to map pin names to a metal layer. Latest versions are in the mentioned folder.

Importing to Cadence
From the ICFB window, File->Import->Steam. Set input file as your exported gds from Encounter. Set top Cell Name and Library Name as appropriate. Click on the User-Defined Data button. Set the layer map table to cds2gds.map (instead of encoutner2virtuoso.map from tutorial). Click on the Options button. Select //change [ ] to <>// in the import options. Click OK

Fix Layout Issues
Replace std cell library to cg_lib13_wsl using search and replace in Virtuoso (just don't replace the vias). Form might look like this: (TODO)

__Pin fix:__ You need to change the pins to actual electrical pins. 1. In LSW, make only metal pin layers selectable. 2. In layout, delete all labels except those you want as pins 3. In Virtuoso, Create->Pins From Labels. Click OK with default options.

__DRC fix:__ The pins are only half covered by metal upon import. Jeremy wrote a skill function to fix this. The skill file is CoverPinsWithMetal.il from the synthesis_files folder. To run: 1. In icfb, type: load("[path]/CoverPinsWithMetal.il") 2. In icfb, type: CoverPinsWithMetal("[library name]" "[cell name]")

Import Map File as Schematic
We need a schematic to LVS our place and route layout against. Cadence has a tool to generate a schematic from your map file. 1. Run from ICFB File->Import->Verilog 2. Add your map file to the //Verilog Files to Import// box (full path required, or click the Add button) 3. Target library should be where your place and route layout is, and the cell name should match. 4. Set //Reference library// to cg_lib13_wsl, import view //Schematic// from the drop down menu 5. Check the //Import// button 6. Fix VDD and GND to vdd! and gnd!, and click OK.

Running DRC, LVS
For LVS, you may need to filter out cdsThru devices: In the LVS window, click modify avCompareRules -> Network -> Filter Device -> Check Use In Run -> Check Schematic In the textbox add: filterDevice("cds_thru" short("src" "dst"))