proj_rfid_ic

RFID Tag IC Project
Update Oct 2010: the RFID Tag Verilog Code is now an open source project. We are using the online repository []. A wiki page on the Verilog Code is setup here: RFID Verilog Code

In Nov 2008, Dan and Azin taped out an RFID tag IC including 915 mhz RF rectifier / charge pump, low power analog components including bandgap, regulator, and RFID demodulator as well as a EPC Class 1 Generation 2 digital core.

Design link: /atm/mead/projects/wsl/wisp_soc/

Full chip: designs/2008_11_final_v2

Verilog: With uC interface: myverilog With fifo: myverilog_v2

Notes: 1. Cell references likely point to ~yeagerd. A quick find and replace in Cadence will fix this.

Bug List: 1. FIFO doesn't synthesize properly - perhaps in/out bus bits are out of order. 2. ADC shorts references together when not powered. Both designs share reference pins -> both must be powered. 3. V1 requires V2's configuration shift register.